| Autor: |
Rachid Elgouri, Mohamed Chentouf, Jalal Benallal, Lekbir Cherif, Nabil Hmina, Mohammed Darmi |
| Rok vydání: |
2018 |
| Předmět: |
|
| Zdroj: |
CIST |
| DOI: |
10.1109/cist.2018.8596605 |
| Popis: |
Layer promotion is a new technique introduced recently for timing optimization at physical implementation stage of an Integrated Circuit (IC). In this paper, we will use the same idea to reduce the power consumption on the interconnection. We implemented the technique and obtained experimental results on a high-speed design made with 7nm technology node. The success criteria are to achieve the highest power reduction without degrading the circuit performance and keep having a good routing of the interconnection. The new nets re-routing power-aware performs an improvement of 20% of total data nets power and a 6% of the entire design total power. This reduction is achieved by optimizing the routing by 40% of data nets that consume more than 92% of the total power in the interconnection. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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