A 0.6 V Low-Power Wide-Range Delay-Locked Loop in 0.18 $\mu$m CMOS

Autor:	Liang-Hung Lu, Chung-Ting Lu, Hsieh-Hung Hsieh
Rok vydání:	2009
Předmět:	Physics business.industry Detector Phase (waves) Electrical engineering Hardware_PERFORMANCEANDRELIABILITY Condensed Matter Physics Power (physics) Loop (topology) CMOS Control theory Delay-locked loop Hardware_INTEGRATEDCIRCUITS Electrical and Electronic Engineering business Voltage
Zdroj:	IEEE Microwave and Wireless Components Letters. 19:662-664
ISSN:	1558-1764 1531-1309
DOI:	10.1109/lmwc.2009.2029752
Popis:	In this letter, a delay-locked loop (DLL) suitable for low-power and low-voltage operations is presented. To overcome the performance limitations, such as a restricted locking range and elevated output jitters, a novel voltage-controlled delay cell and a phase/frequency detector with a start controller are employed in the proposed DLL. Using a standard 0.18 mum CMOS process, the fabricated circuit exhibits a locking range from 85 to 550 MHz. The measured peak-to-peak and rms jitters at 550 MHz are 25.6 and 3.8 ps, respectively. Operated at a supply voltage of 0.6 V, the power consumption of the DLL circuit varies from 2.4 to 4.2 mW within the entire locking range.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::4829898a38b1a04c92a910d832dce3d0 https://doi.org/10.1109/lmwc.2009.2029752 Zobrazit plný text záznamu