Digital Error Correction for a 10-Bit Straightforward SAR ADC
| Autor: | Kang-Yoon Lee, Behnam Samadpoor Rikan, Dongsoo Lee, Sung-Han Do, Hamed Abbasizadeh |
|---|---|
| Rok vydání: | 2015 |
| Předmět: |
Computer science
business.industry Electrical engineering Digital error correction Successive approximation ADC Hardware_PERFORMANCEANDRELIABILITY law.invention Capacitor CMOS law Power consumption Signal Processing Hardware_INTEGRATEDCIRCUITS Electronic engineering Redundancy (engineering) Figure of merit Electrical and Electronic Engineering business |
| Zdroj: | IEIE Transactions on Smart Processing and Computing. 4:51-58 |
| ISSN: | 2287-5255 |
| DOI: | 10.5573/ieiespc.2015.4.1.051 |
| Popis: | This paper proposes a 10-b SAR ADC. To increase the conversion speed and reduce the power consumption and area, redundant cycles were implemented digitally in a capacitor DAC. The capacitor DAC algorithm was straightforward switching, which included digital error correction steps. A prototype ADC was implemented in CMOS 0.18-μm technology. This structure consumed 140μW and achieved 59.4-dB SNDR at 1.25MS/s under a 1.8-V supply. The figure of merit (FOM) was 140fJ/conversion-step. |
| Databáze: | OpenAIRE |
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