105nm Gate length pMOSFETs with high-K and metal gate fabricated in a Si process line on 200mm GeOI wafers
| Autor: | Chrystel Deguet, K. Romanjek, Laurent Clavelier, S. Soliveres, R. Truche, M. Vinet, A. Pouydebasque, G. Le Carval, M.-C. Roure, C. Le Royer, H. Grampeix, Loic Sanchez, Claude Tabone, Simon Deleonibus, J.M. Hartmann |
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| Rok vydání: | 2008 |
| Předmět: |
Materials science
Silicon business.industry Transconductance chemistry.chemical_element Nanotechnology Condensed Matter Physics Electronic Optical and Magnetic Materials Ion implantation chemistry MOSFET Materials Chemistry Optoelectronics Wafer Electrical and Electronic Engineering business Metal gate Current density High-κ dielectric |
| Zdroj: | Solid-State Electronics. 52:1285-1290 |
| ISSN: | 0038-1101 |
| DOI: | 10.1016/j.sse.2008.04.019 |
| Popis: | We report on the fabrication and electrical characterization of deep sub-micron (gate length down to 105 nm) GeOI pMOSFETs. The Ge layer obtained by hetero-epitaxy on Si wafers has been transferred using the Smart Cut TM process to fabricate 200 mm GeOI wafers with Ge thickness down to 60–80 nm. A full Si MOS compatible pMOSFET process was implemented with HfO 2 /TiN gate stack. The electrical characterization of the fabricated devices and the systematic analysis of the measured performances ( I ON , I OFF , transconductance, low field mobility, S , DIBL) demonstrate the potential of pMOSFET on GeOI for advanced technological nodes. The dependence of these parameters have been analyzed with respect to the gate length, showing very good transport properties ( μ h ∼ 250 cm 2 /V/s, I ON = 436 μA/μm for L G = 105 nm), and OFF current densities comparable or better than those reported in the literature. |
| Databáze: | OpenAIRE |
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