Chip-Level Substrate Coupling Analysis with Reference Structures for Verification
| Autor: | Daisuke Kosaka, Atsushi Iwata, Makoto Nagata, Yoshitaka Murasaka |
|---|---|
| Rok vydání: | 2007 |
| Předmět: |
Digital electronics
Substrate coupling Materials science business.industry Applied Mathematics Electrical engineering Hardware_PERFORMANCEANDRELIABILITY Substrate (printing) Chip Computer Graphics and Computer-Aided Design Noise (electronics) Parasitic capacitance CMOS Signal Processing Hardware_INTEGRATEDCIRCUITS Optoelectronics Electrical and Electronic Engineering business Electronic circuit |
| Zdroj: | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. :2651-2660 |
| ISSN: | 1745-1337 0916-8508 |
| DOI: | 10.1093/ietfec/e90-a.12.2651 |
| Popis: | Chip-level substrate coupling analysis uses F-matrix computation with slice-and-stack execution to include highly concentrated substrate resistivity gradient. The technique that has been applied to evaluation of device-level isolation structures against substrate coupling is now developed into chip-level substrate noise analysis. A time-series divided parasitic capacitance (TSDPC) model is equivalent to a transition controllable noise source (TCNS) circuit that captures noise generation in a CMOS digital circuit. A reference structure incorporating TCNS circuits and an array of on-chip high precision substrate noise monitors provides a basis for the verification of chip-level analysis of substrate coupling in a given technology. Test chips fabricated in two different wafer processings of 0.30-μm and 0.18-μm CMOS technologies demonstrate the universal availability of the proposed analysis techniques. Substrate noise simulation achieves no more than 3 dB discrepancy in peak amplitude compared to measurements with 100-ps/100-μV resolution, enabling precise evaluation of the impacts of the distant placements of sensitive devices from sources of noise as well as application of guard ring/band structures. |
| Databáze: | OpenAIRE |
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