A 40 Gb/s Multi-Data-Rate CMOS Transmitter and Receiver Chipset With SFI-5 Interface for Optical Transmission Systems
| Autor: | Kenichi Hosoya, Nobuhiro Kawahara, Risato Ohhira, Hiroshi Yamaguchi, H. Ikeda, Tomoyuki Yamase, Akira Tanabe, Shunichi Kaeriyama, Z. Yamazaki, Sadao Fujita, A. Noda, T. Takahashi, Hiroaki Shoda, Yasushi Amamiya, Kenichiro Hijioka, Hidemi Noguchi, M. Okamoto, S. Tomari, Shinichi Tanaka |
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| Rok vydání: | 2009 |
| Předmět: | |
| Zdroj: | IEEE Journal of Solid-State Circuits. 44:3568-3579 |
| ISSN: | 1558-173X 0018-9200 |
| Popis: | A fully integrated 40 Gb/s transmitter and receiver chipset with SFI-5 interface is implemented in a 65 nm CMOS technology and mounted in a plastic BGA package. The transmitter chip provides good jitter performance with a 40 GHz full-rate clock architecture that alleviates pattern-dependent jitter and eliminates duty cycle dependence. The measured RMS jitter on the output is 570 fs to 900 fs over the range of 39.8 Gb/s to 44.6 Gb/s with a 231-1 PRBS pattern. The receiver chip operates over the range of 37 Gb/s to 41 Gb/s. The measured RMS jitter on the recovered clock is 359 fs to 450 fs. By taking advantage of CMOS technology, each chip achieves low power consumption of 2.8 W and full integration of SFI-5 functions, PRBS generators/error checkers, a DPSK precoder/decoder, and control interfaces in a 4.9 × 5.2 mm2 die. |
| Databáze: | OpenAIRE |
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