Implementation of Yolo-v2 Image Recognition and Other Testbenches for a CNN Accelerator
| Autor: | Hyun-Mi Kim, Kyoung Seon Shin, Young-Su Kwon, Chan Kim, Minseok Choi, Yong Cheol Peter Cho, Jeongmin Yang, Jinho Han, In San Jeon, Chun-Gi Lyuh, Jaehoon Chung |
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| Rok vydání: | 2019 |
| Předmět: |
Floating point
Computer science business.industry Deep learning Systolic array 02 engineering and technology 010501 environmental sciences Chip 01 natural sciences 020202 computer hardware & architecture Convolution 16-bit Software 0202 electrical engineering electronic engineering information engineering Computer vision Artificial intelligence business Field-programmable gate array 0105 earth and related environmental sciences |
| Zdroj: | ICCE-Berlin |
| DOI: | 10.1109/icce-berlin47944.2019.8966213 |
| Popis: | An implementation of Yolo-v2 image recognition and other testbenches for a deep learning accelerator is presented. This chip is the initial version of our on-going effort for a higher performance accelerator development. The accelerator is based on a systolic array and can handle convolution and max-pooling layer in a combined way or separately using 16 bit floating-point data. It also supports inner-product and LSTM layers. For demonstration and as one of the design verification testbenches, we implemented Yolo-v2 image recognition for 80 object classes. We converted the Yolo-v2 software to 16 bit floating point version and used it in the simulation and FPGA experiment during the chip development. Several other testbenches were designed and used to test various networks. In this paper, the accelerator’s architecture and the Yolo-v2 implementation on our FPGA board including camera and LCD is explained, including the software implementation. Some analyses on the measured and estimated performance is shown. |
| Databáze: | OpenAIRE |
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