A 6.4/3.2/1.6 Gb/s low power interface with all digital clock multiplier for on-the-fly rate switching

Autor:	Makarand Shirasgaonkar, Wayne Dettloff, Teva Stone, Jared L. Zerbe, Brian Tsang, Kambiz Kaviani, Kashinath Prabhu, Masum Hossain, Barry Daly, John Eble
Rok vydání:	2012
Předmět:	Clock signal Clock domain crossing Computer science Underclocking Electronic engineering Source-synchronous Clock gating Digital clock manager Hardware_ARITHMETICANDLOGICSTRUCTURES CPU multiplier Digital clock
Zdroj:	CICC
DOI:	10.1109/cicc.2012.6330579
Popis:	A dynamic rate adjustable interface is designed a 40-nm LP CMOS process. On-the-fly dynamic rate change is enabled by an all-digital frequency multiplier that detects a reference frequency change, and accordingly provides 4× multiplied clock without any idle time. The clock multiplier, along with matched source synchronous clocking and clock equalization, allows blind reference clock shifting to scale the data rate from 1.6 to 6.4 Gb/s within 6.125ns without idle time or bit errors during transitions. The interface efficiency is 2.6 mW/Gb/s @6.4 Gb/s & 3.4 mW/Gb/s @3.2 Gb/s when using reduced clock swing and external transmitter swing at the reduced data rates.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::46a91d6a255d88b1dfda4287e8de35bd https://doi.org/10.1109/cicc.2012.6330579 Zobrazit plný text záznamu