The implementation of POWER7TM: A highly parallel and scalable multi-core high-end server processor
| Autor: | Sam Gat-Shang Chu, S. Weitzel, Victor Zyuban, Dieter Wendel, James Allan Kahle, Roland Frech, Ronald Nick Kalla, Joshua Friedrich, Scott A. Taylor, Saiful Islam, Balaram Sinharoy, Robert Cargoni, Joachim Clables, William J. Starke |
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| Rok vydání: | 2010 |
| Předmět: |
Random access memory
Multi-core processor business.industry Computer science Bandwidth (signal processing) Transistor Hardware_PERFORMANCEANDRELIABILITY law.invention Capacitor CMOS law Embedded system Scalability Hardware_INTEGRATEDCIRCUITS Static random-access memory business Dram Computer hardware |
| Zdroj: | ISSCC |
| DOI: | 10.1109/isscc.2010.5434074 |
| Popis: | The next processor of the POWER ™ family, called POWER7™ is introduced. Eight quad-threaded cores are integrated together with two memory controllers and high-speed system links on a 567mm2 die, employing 1.2B transistors in 45nm CMOS SOI technology [4]. High on-chip performance and therefore bandwidth is achieved using 11 layers of low-к copper wiring and devices with enhanced dual-stress liners. The technology features deep trench [DT] capacitors that are used to build the 32MB embedded DRAM L3 based on a 0.067µm2 DRAM cell. DT capacitors are used also to reduce on-chip voltage-island supply noise. Focusing on speed, the dual-supply ripple-domino SRAM concepts follows the schemes described elsewhere. |
| Databáze: | OpenAIRE |
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