Parasitic resistance and leakage reduction by raised source / drain extention fabricated with cluster ion implantation and millisecond annealing

Autor:	T. Ikezawa, Kazuya Uejima, K. Yako, Toyoji Yamamoto, Masami Hane
Rok vydání:	2008
Předmět:	Millisecond Ion implantation Materials science business.industry Annealing (metallurgy) Logic gate Thermal resistance Parasitic element Optoelectronics business Capacitance Leakage (electronics)
Zdroj:	2008 16th IEEE International Conference on Advanced Thermal Processing of Semiconductors.
DOI:	10.1109/rtp.2008.4690561
Popis:	We designed and fabricated sub-30 nm gate length pMOSFETs developing the raised source/drain extension (RSDext) process. Our process features usages of cluster-ion (B 18 H 22 ) implantation and high-temperature millisecond annealing processes and a facet-structure-control of the RSDext of less than 10 nm thickness for suppressing a fringe capacitance increase for the “effective” ultra-shallower junction formation. As the results, experimentally obtained our pMOSFETs with raised source/drain extension show almost the same L MIN , 1/2 times lower parasitic resistance and lower junction leakage.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::45d5a05c738fee71eb186968e9e0af79 https://doi.org/10.1109/rtp.2008.4690561 Zobrazit plný text záznamu