VThreads: A novel VLIW chip multiprocessor with hardware-assisted PThreads
| Autor: | David Stevens, Vincent M. Dwyer, Vassilios Chouliaras |
|---|---|
| Rok vydání: | 2016 |
| Předmět: |
POSIX Threads
Computer Networks and Communications Computer science business.industry 020208 electrical & electronic engineering Task parallelism Multiprocessing 02 engineering and technology Parallel computing Thread (computing) 020202 computer hardware & architecture Artificial Intelligence Hardware and Architecture Very long instruction word Embedded system VHDL 0202 electrical engineering electronic engineering information engineering Instruction-level parallelism business computer Software Computer hardware computer.programming_language |
| Zdroj: | Microprocessors and Microsystems. 47:466-485 |
| ISSN: | 0141-9331 |
| Popis: | We discuss VThreads, a novel VLIW CMP with hardware-assisted shared-memory Thread support. VThreads supports Instruction Level Parallelism via static multiple-issue and Thread Level Parallelism via hardware-assisted POSIX Threads along with extensive customization. It allows the instantiation of tightly-coupled streaming accelerators and supports up to 7-address Multiple-Input, Multiple-Output instruction extensions. VThreads is designed in technology-independent Register-Transfer-Level VHDL and prototyped on 40 nm and 28 nm Field-Programmable gate arrays. It was evaluated against a PThreads-based multiprocessor based on the Sparc-V8 ISA. On a 65 nm ASIC implementation VThreads achieves up to x7.2 performance increase on synthetic benchmarks, x5 on a parallel Mandelbrot implementation, 66% better on a threaded JPEG implementation, 79% better on an edge-detection benchmark and ∼13% improvement on DES compared to the Leon3MP CMP. In the range of 2 to 8 cores, VThreads demonstrates a post-route (statistical) power reduction between 65% and 57% at an area increase of 1.2%–10% for 1–8 cores, compared to a similarly-configured Leon3MP CMP. This combination of micro-architectural features, scalability, extensibility, hardware support for low-latency PThreads, power efficiency and area make the processor an attractive proposition for low-power, deeply-embedded applications requiring minimum OS support. |
| Databáze: | OpenAIRE |
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