(Invited) Metal Gate/High-κ Dielectric Gate Stack Reliability; or How I Learned to Live with Trappy Oxides

Autor: Siddarth A. Krishnan, Eduard A. Cartier, Barry Linder
Rok vydání: 2013
Předmět:
Zdroj: ECS Transactions. 53:187-192
ISSN: 1938-6737
1938-5862
Popis: Over the last couple of scaling generations the gate stack in leading edge technology has migrated from Poly-Si and SiON to a metal gate with a bi-layer of a Hafnium based dielectric with a SiON interlayer (IL). This switch yielded immediate gains in gate leakage (Ig) and reliability, allowing a thinning of the inversion thickness (tinv) from ~20Å to less than 14Å. Even though gate length scaling and performance would drive further thinning of the dielectric stack, reliability considerations limit this. Understanding the fundamental reliability mechanisms enables mitigation with process changes and an optimization of reliability, performance, and operating voltage (Vmax). This paper will explore the main reliability mechanisms that are limiting scaling and the processes that improve reliability. Furthermore, the relationship between device level reliability and circuit reliability will be broached with ring oscillator data that shines light on the dominant reliability mechanism limiting Vmax.
Databáze: OpenAIRE