A High Performance Dual Stage Face Detection Algorithm Implementation using FPGA Chip and DSP Processor

Autor:	M V Ganeswara Rao, P Ravi Kumar, T Balaji
Rok vydání:	2022
Předmět:	Artificial Intelligence Computer Networks and Communications Computer Vision and Pattern Recognition Computer Science Applications Information Systems
Zdroj:	Journal of Information Systems and Telecommunication (JIST). 10:241-248
ISSN:	2322-1437
DOI:	10.52547/jist.31803.10.40.241
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::456cf1f39209bc2bb5a0fe3246c94724 https://doi.org/10.52547/jist.31803.10.40.241 Zobrazit plný text záznamu