A PLL configuration for reducing both incoming and inherent jitters
| Autor: | Yuhta Egashira, Hitoshi Kondoh, Fuminori Kobayashi |
|---|---|
| Rok vydání: | 2009 |
| Předmět: |
Engineering
business.industry ComputerSystemsOrganization_COMPUTER-COMMUNICATIONNETWORKS Feed forward Reduction (complexity) Phase-locked loop Control theory Hardware_INTEGRATEDCIRCUITS Electronic engineering ComputerSystemsOrganization_SPECIAL-PURPOSEANDAPPLICATION-BASEDSYSTEMS Sensitivity (control systems) business Field-programmable gate array Loop gain Jitter |
| Zdroj: | ICECS |
| Popis: | In order to reduce jitters, both incoming and inherent, this article proposes a novel configuration. Feed-forward compensator improves jitter filtration, free from constraints on loop gain for reducing inherent jitters. Its effectiveness is verified on a prototype implemented on an FPGA, and experiments as a multiply-by-50 synthesizer result in 30-times reduction of inherent jitters and in halving of incoming jitters. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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