Design and implementation of 4 bit binary weighted current steering DAC

Autor:	Amisha P. Naik, Jayeshkumar J. Patel
Rok vydání:	2020
Předmět:	Differential nonlinearity Least significant bit General Computer Science Transmission gate CMOS Computer science Electronic engineering Electrical and Electronic Engineering 4-bit NMOS logic PMOS logic Voltage
Zdroj:	International Journal of Electrical and Computer Engineering (IJECE). 10:5642
ISSN:	2722-2578 2088-8708
DOI:	10.11591/ijece.v10i6.pp5642-5649
Popis:	A compact current-mode Digital-to-Analog converter (DAC) suitable for biomedical application is repesented in this paper .The designed DAC is binary weighted in 180nm CMOS technology with 1.8V supply voltage. In this implementation, authors have focused on calculaton of Non linearity error say INL and DNL for 4 bit DAC having various type of switches: NMOS, PMOS and Transmission Gate. The implemented DAC uses lower area and power compared to unary architecture due to absence of digital decoders. The desired value of Integrated non linearity (INL) and Differential non linearity (DNL) for DAC for are within a range of +0.5LSB. Result obtained in this works for INL and DNL for the case DAC using Transmission Gate is +0.34LSB and +0.38 LSB respectively with 22mW power dissipation.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::44ff752affb677a1be156bf795a96970 https://doi.org/10.11591/ijece.v10i6.pp5642-5649 Zobrazit plný text záznamu