Analysis of the Programmable Soft IP-cores Implementation for FPGAs
| Autor: | V.M. Khvatov, D. A. Zheleznikov, S.V. Gavrilov |
|---|---|
| Rok vydání: | 2021 |
| Předmět: |
010302 applied physics
Adder business.industry Computer science Soft IP 02 engineering and technology 01 natural sciences 020202 computer hardware & architecture Logic gate Embedded system 0103 physical sciences Subtractor Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Routing (electronic design automation) Field-programmable gate array business Hardware_REGISTER-TRANSFER-LEVELIMPLEMENTATION Hardware_LOGICDESIGN Shift register Block (data storage) |
| Zdroj: | 2021 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (ElConRus). |
| DOI: | 10.1109/elconrus51938.2021.9396572 |
| Popis: | Soft programmable IP-cores are usually used to speed up the integrated circuits design in FPGA. Soft blocks are formed from programmable logical FPGA elements independently from specific location on the FPGA and do not have pre-routed paths. Some FPGA architectures contain specialized resources to improve IP-cores design efficiency. It is necessary to consider these resources in CAD methods and components development.The paper presents the comparative analysis of two types of soft IP-cores implementation. The first type utilizes the architectural features of the FPGA due to a special block library. The second one obtains the results of automatic synthesis in a standard elements basis. The final size of designed IP-cores and the amount of utilized routing resources are compared. Also, the paper describes the specifics of the FPGA routing resources usage and the other implementation issues of such soft IP-cores as an n-bit adder / subtractor, an up-to-N counter, and a shift register. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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