27.6 A 4GS/s 13b pipelined ADC with capacitor and amplifier sharing in 16nm CMOS
| Autor: | Acer Wei-Te Chou, Young Shin, Hung-Sen Huang, Tao Wang, Juo-Jung Hung, Po Tang Yang, Chun-Ying Chen, Massimo Brandolini, Cheng-Hsun Yang, Tianwei Li, Sha-Ting Lin, Ardie Venes, Dongsoo Koh, Jiangfeng Wu, Gregory Unruh, Mo M. Zhang, Rong Wu, Qingqi Dou, Giuseppe Cusmai, Sunny Raj Dommaraju, H. Mohan Geddada, Xi Chen, Wei-Ting Lin |
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| Rok vydání: | 2016 |
| Předmět: |
Engineering
Comparator business.industry Amplifier 020208 electrical & electronic engineering 020206 networking & telecommunications 02 engineering and technology law.invention Noise Capacitor CMOS Sampling (signal processing) law Distortion 0202 electrical engineering electronic engineering information engineering Electronic engineering Operational amplifier Hardware_ARITHMETICANDLOGICSTRUCTURES business |
| Zdroj: | ISSCC |
| Popis: | In recent years, we have seen the emergence of multi-GS/s medium-to-high-resolution ADCs. Presently, SAR ADCs dominate low-speed applications and time-interleaved SARs are becoming increasingly popular for high-speed ADCs [1,2]. However the SAR architecture faces two key problems in simultaneously achieving multi-GS/s sample rates and high resolution: (1) the fundamental trade-off of comparator noise and speed is limiting the speed of single-channel SARs, and (2) highly time-interleaved ADCs introduce complex lane-to-lane mismatches that are difficult to calibrate with high accuracy. Therefore, pipelined [3] and pipelined-SAR [4] remain the most common architectural choices for high-speed high-resolution ADCs. In this work, a pipelined ADC achieves 4GS/s sample rate, using a 4-step capacitor and amplifier-sharing front-end MDAC architecture with 4-way sampling to reduce noise, distortion and power, while overcoming common issues for SHA-less ADCs. |
| Databáze: | OpenAIRE |
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