| Popis: |
A wafer level package (WLP) has been developed as a cost effective packaging method compared to the /spl mu/BGA package, and especially applied to the Rambus DRAM (RDRAM) package. The maximum allowable thickness of the stress buffer layer on the WLP is limited to about 20 /spl mu/m, due to the limitation of the present spin coating process technology. Hence, the thickness of the stress buffer layer is much smaller than that of the elastomer (175 pm) used as a dielectric layer in the /spl mu/BGA package. Consequently, due to this extremely small distance between the metal traces on the WLP and the silicon substrate, the capacitive loading of the WLP on the RIMM (Rambus in-line memory module) is significantly increased. The increased capacitive loading by the WLP results in a decrease in the effective line impedance and an increase in the propagation delay on the RIMM, while the target line impedance on the RIMM is 28 /spl Omega//spl plusmn/10%. Therefore, careful design considerations are required at the package design level and at the module design level, to compensate for the increased capacitive loading by the WLP. In this paper, we firstly introduce the equivalent circuit model of the WLP interconnection lines using the S-parameter measurement in the microwave frequency region up to 5 GHz. Then, we suggest the electrical design methodology of the WLP and the module to compensate for the increased loading capacitance of the WLP. |
