A 2.267-Gb/s, 93.7-pJ/bit Non-Binary LDPC Decoder With Logarithmic Quantization and Dual-Decoding Algorithm Scheme for Storage Applications
| Autor: | Dejan Markovic, Yuta Toriyama |
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| Rok vydání: | 2018 |
| Předmět: |
Computer science
Error floor 020206 networking & telecommunications 02 engineering and technology Coding gain 020202 computer hardware & architecture Reduction (complexity) 0202 electrical engineering electronic engineering information engineering Code (cryptography) Binary code Electrical and Electronic Engineering Low-density parity-check code Algorithm Throughput (business) Decoding methods |
| Zdroj: | IEEE Journal of Solid-State Circuits. 53:2378-2388 |
| ISSN: | 1558-173X 0018-9200 |
| DOI: | 10.1109/jssc.2018.2832851 |
| Popis: | Non-binary low-density parity-check (NB-LDPC) codes are a promising class of error-correcting codes that provide excellent coding gain beyond that of their binary counterparts. However, their decoding complexity has thus far limited practicality. We present an NB-LDPC decoder with information throughput of 2.267 Gb/s and power consumption of 212.4 mW, yielding an energy efficiency of 93.7 pJ/bit, implemented in 40-nm CMOS technology. The employed code is long and high-rate without degree-2 variable nodes, resulting in a low error floor and making the code appropriate for storage applications. A logarithmic quantization scheme is proposed to enable aggressive wordlength reduction to alleviate hardware complexity. In addition, a dual-decoding algorithm scheme is employed to alleviate the computational complexity of decoding, realized in an efficient architecture with high parallelism and avoidance of idle clock cycles. |
| Databáze: | OpenAIRE |
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