SRAM bitline circuits on PD SOI: advantages and concerns
| Autor: | Shao-Fu S. Chu, Somnuk Ratanaphanyarat, Roy Childs Flaker, Jente B. Kuang, G.G. Shahidi, Lawrence F. Wagner, L. Hsu, M.J. Saccamango |
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| Rok vydání: | 1997 |
| Předmět: |
Hardware_MEMORYSTRUCTURES
Materials science Silicon on insulator Hardware_PERFORMANCEANDRELIABILITY Capacitance Diffusion capacitance Threshold voltage CMOS Hardware_INTEGRATEDCIRCUITS Electronic engineering Static random-access memory Electrical and Electronic Engineering Hardware_LOGICDESIGN Electronic circuit Floating body effect |
| Zdroj: | IEEE Journal of Solid-State Circuits. 32:837-844 |
| ISSN: | 0018-9200 |
| DOI: | 10.1109/4.585285 |
| Popis: | This paper presents a study of sub-0.25-/spl mu/m CMOS SRAM bitline circuitry on partially depleted (PD) silicon-on-insulator (SOI) technology. SOI implementations outperform conventional bulk ones due to significant reduction of collective device junction capacitance on the bitlines. Floating body effects are investigated for both read and write cycles. Array content dependent behaviors are identified for the first time and analyzed with worst-case temporal and spatial pattern combinations. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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