Non-planar, multi-gate InGaAs quantum well field effect transistors with high-K gate dielectric and ultra-scaled gate-to-drain/gate-to-source separation for low power logic applications
| Autor: | Matthew V. Metz, G. Dewey, Roza Kotlyar, L. Pan, Jack Portland Kavalieros, Uday Shah, W. K. Liu, W. Rachmady, R. Pillarisetty, Niloy Mukherjee, D. Lubyshev, Robert S. Chau, Benjamin Chu-Kung, K. Millard, J. M. Fastenau, Marko Radosavljevic |
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| Rok vydání: | 2010 |
| Předmět: |
Materials science
business.industry Gate dielectric Hardware_PERFORMANCEANDRELIABILITY Dielectric chemistry.chemical_compound chemistry Logic gate Low-power electronics Parasitic element Hardware_INTEGRATEDCIRCUITS Optoelectronics Field-effect transistor business Indium gallium arsenide Hardware_LOGICDESIGN High-κ dielectric |
| Zdroj: | 2010 International Electron Devices Meeting. |
| DOI: | 10.1109/iedm.2010.5703306 |
| Popis: | In this work, non-planar, multi-gate InGaAs quantum well field effect transistors (QWFETs) with high-K gate dielectric and ultra-scaled gate-to-drain and gate-to-source separations (L SIDE ) of 5nm are reported for the first time. The high-K gate dielectric formed on this non-planar device structure has the expected thin TOXE of 20.5A with low J G , and high quality gate dielectric interface. The simplified S/D scheme is needed for the non-planar architecture while achieving significant reduction in parasitic resistance. Compared to the planar high-K InGaAs QWFET with similar T OXE , the non-planar, multi-gate InGaAs QWFET shows significantly improved electrostatics due to better gate control. The results of this work show that non-planar, multi-gate device architecture is an effective way to improve the scalability of III–V QWFETs for low power logic applications. |
| Databáze: | OpenAIRE |
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