Models and Algorithmic Limits for an ECC-Based Approach to Hardening Sub-100-nm SRAMs
| Autor: | R. Naseer, Scott D. Stansberry, Lloyd W. Massengill, M.A. Bajura, J. Sondeen, S. DasGupta, Y. Boulghassoul, Arthur F. Witulski, Jeffrey Draper, John Damoulakis |
|---|---|
| Rok vydání: | 2007 |
| Předmět: |
Nuclear and High Energy Physics
Hardware_MEMORYSTRUCTURES Computer science Memory scrubbing Hardware_PERFORMANCEANDRELIABILITY Upset Coding gain Reliability engineering Majority logic decoding Soft error Nuclear Energy and Engineering Electronic engineering Bit error rate Static random-access memory Hardware_ARITHMETICANDLOGICSTRUCTURES Electrical and Electronic Engineering Data scrubbing |
| Zdroj: | IEEE Transactions on Nuclear Science. 54:935-945 |
| ISSN: | 0018-9499 |
| DOI: | 10.1109/tns.2007.892119 |
| Popis: | A mathematical bit error rate (BER) model for upsets in memories protected by error-correcting codes (ECCs) and scrubbing is derived. This model is compared with expected upset rates for sub-100-nm SRAM memories in space environments. Because sub-100-nm SRAM memory cells can be upset by a critical charge (Qcrit) of 1.1 fC or less, they may exhibit significantly higher upset rates than those reported in earlier technologies. Because of this, single-bit-correcting ECCs may become impractical due to memory scrubbing rate limitations. The overhead needed for protecting memories with a triple-bit-correcting ECC is examined relative to an approximate 2X ldquoprocess generationrdquo scaling penalty in area, speed, and power. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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