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This paper introduces a new method for the selection of optinuxl probing points in chip-internal e-beam testing by applying a set ofprobingpoint selection rules to the complete area of the desired wire. Conznzvrcially available design rule check (DRC) tools are used to perform the required topological operations. For easy adaption to different technologies, a rule definition language hus been developed to allow forthedefinition ofrules independent of the utilized DRCtool. Theyrobingpointselection is such thut loculfield eflects, crosstalk and circuit structure influences are nzininzized. |