InAs FinFETs With Hfinnm Fabricated Using a Top–Down Etch Process
| Autor: | Martin Christopher Holland, Matthias Passlack, Yee-Chia Yeo, Peter Ramvall, Stephen Thoms, I.G. Thayne, T. Vasen, Douglas Macintyre, R. Droopad, Shyh-Wei Wang, R. Contreras-Guerrero, J.S. Rojas-Ramirez, Richard Kenneth Oxland, Xu Li, Gerben Doornbos, Carlos H. Diaz, Chang Yen-An, S. W. Chang |
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| Rok vydání: | 2016 |
| Předmět: |
010302 applied physics
Fin Materials science Gate length Analytical chemistry Fin width Heterojunction Nanotechnology 02 engineering and technology 021001 nanoscience & nanotechnology 01 natural sciences Electronic Optical and Magnetic Materials Planar Etching (microfabrication) 0103 physical sciences Fin height Electrical and Electronic Engineering 0210 nano-technology |
| Zdroj: | IEEE Electron Device Letters. 37:261-264 |
| ISSN: | 1558-0563 0741-3106 |
| Popis: | We report the first demonstration of InAs FinFETs with fin width $\textrm {W}_{{\mathrm{fin}}}$ in the range 25–35 nm, formed by inductively coupled plasma etching. The channel comprises defect-free, lattice-matched InAs with fin height $\textrm {H}_{{\mathrm{fin}}}=20$ nm controlled by the use of an etch stop layer incorporated into the device heterostructure. For a gate length $\textrm {L}_{{{\textrm {g}}}}=1~\mu \text{m}$ , peak transconductance $\textrm {g}_{{{\textrm {m},{\mathrm{ peak}}}}}=1430~\mu \text{S}/\mu \text{m}$ is measured at $\textrm {V}_{{\textrm {d}}}=0.5$ V demonstrating that electron transport in InAs fins can match planar devices. |
| Databáze: | OpenAIRE |
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