PLL-based BiCMOS on-chip clock generator for very high-speed microprocessor

Autor:	Kozaburo Kurita, Tetsuo Nakano, Takashi Hotta, N. Kitamura
Rok vydání:	1991
Předmět:	Engineering Synchronous circuit business.industry Clock rate Clock gating Hardware_PERFORMANCEANDRELIABILITY Digital clock manager Clock skew Clock domain crossing Hardware_INTEGRATEDCIRCUITS Electronic engineering Clock generator Electrical and Electronic Engineering business CPU multiplier
Zdroj:	IEEE Journal of Solid-State Circuits. 26:585-589
ISSN:	0018-9200
DOI:	10.1109/4.75059
Popis:	Described is a phase-locked loop (PLL)-based BiCMOS on-chip clock generator (PCG), which is used to generate an internal clock synchronized to a reference clock from outside the chip. In order to obtain a very wide operation bandwidth, it is proposed that the PCG include a compensation circuit for voltage-controlled oscillator (VCO) operation. The compensation circuit varies the oscillation bandwidth of the VCO according to the reference clock frequency, preventing the expected oscillation frequency from being outside the oscillation bandwidth. The PCG is designed and fabricated with 1.0 mu m BiCMOS technology, and it achieves an operation bandwidth of 3 to 90 MHz. >
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::426703440c619c5493761356dd409248 https://doi.org/10.1109/4.75059 Zobrazit plný text záznamu