A 0.5 nJ/Pixel 4 K H.265/HEVC Codec LSI for Multi-Format Smartphone Applications
| Autor: | Chun-Chia Chen, Tsu-Ming Liu, Min-Hao Chiu, Tung-Hsing Wu, Chi-cheng Ju, Wei-Cing Li, Yen-Chieh Lai, Yi-Hsin Huang, Peng-Hao Wang, Yen-Chao Huang, Chih-Ming Wang, Ping Chao, Hsiu-Yi Lin, Ming-Long Wu, Meng-Jye Hu, Yu-Kun Lin, Ting-An Lin, Chia-Yun Cheng, Che-Hong Chen, Sheng-Jen Wang, Shun-Hsiang Chuang, Han-Liang Chou, Chen Lien-Fei, Hue-Min Lin, Yung-Chang Chang, Chih-Da Chien, Kun-bin Lee |
|---|---|
| Rok vydání: | 2016 |
| Předmět: |
Pixel
business.industry Computer science 020208 electrical & electronic engineering Clock rate 02 engineering and technology Chip Embedded system 0202 electrical engineering electronic engineering information engineering Codec 020201 artificial intelligence & image processing Electrical and Electronic Engineering business Computer hardware Decoding methods |
| Zdroj: | IEEE Journal of Solid-State Circuits. 51:56-67 |
| ISSN: | 1558-173X 0018-9200 |
| DOI: | 10.1109/jssc.2015.2465857 |
| Popis: | A 4 K $\,\times\,$ 2 K H.265/HEVC video codec chip supporting 14 video standard formats is implemented on a 1.49 $\,\times\,$ 1.45 mm $^{2}$ die in a 28 nm CMOS process. Several HEVC fast algorithms reduce the coding modes by analyzing the content features leading to over 68.5% and 83% of complexity reduction in intra and inter coding, respectively. A fully parallel processing element (PE) array is adopted in SAO and IP/ME, which reduce number of accesses to SRAM by 48.7% and 78.4%, respectively. A shared memory management unit (MMU) including line-store SRAM pool (LSSP) and data bus translation (DBT) techniques efficiently reuses and packs the neighboring pixels which contribute 71.6% of external bandwidth reduction. This chip achieves 4096 $\,\times\,$ 2160@30 fps HEVC encoding/decoding and consumes 126.73 mW, 0.5 nJ/pixel of energy efficiency, under 494 MHz and 350 MHz of clock frequency, enabling 4 K video services for smart-phone applications. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|