A 12.8-Gb/s/link Tri-Modal Single-Ended Memory Interface
| Autor: | Manish Jain, C. Huang, Keisuke Saito, Wendemagegnehu T. Beyene, Kun-Yung Ken Chang, J. Wei, Deborah Dressier, T. J. Chin, Catherine Chen, Dave Secker, Phuong Le, Vijay Gadde, Chris Madden, Xingchao Yuan, Ting Wu, Chanh Tran, Mahabaleshwara, Sanku Mukherjee, Navin Kumar Mishra, Ling Yang, Leneesh Raghavan, Arul Sendhil, Amir Amirkhany, Hai Lan, Arun Vaidyanath, R. Schmitt, Gundlapalli Shanmukha Srinivas, Shuaeb Fazeel, Mohammad Hekmat, Kambiz Kaviani, Kapil Vyas, Jie Shen |
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| Rok vydání: | 2012 |
| Předmět: | |
| Zdroj: | IEEE Journal of Solid-State Circuits. 47:911-925 |
| ISSN: | 1558-173X 0018-9200 |
| Popis: | This paper presents a tri-modal asymmetric memory controller interface that achieves 12.8-Gbps single-ended (SE) signaling over 3" stripline FR4 traces. The controller can be configured to communicate with commercially available GDDR5 and DDR3 memories at 6.4 and 1.6 Gbps, respectively, with no package change. The interface is equipped with a compact voltage-mode driver with 1-tap pre-emphasis, in the WRITE direction, and a linear equalizer (LEQ) and 1-tap decision feedback equalizer (DFE), in the READ direction, to compensate for channel inter-symbol interference (ISI). The receiver front-end contains a supply noise tracking scheme to mitigate reference voltage (VREF) noise. A tri-VCO PLL and an efficient global clock distribution scheme support a wide range of operating frequencies at low power consumption. Finally, the interface also incorporates two overhead links per byte for data-bus encoding (DBE) experiments to mitigate simultaneous switching noise (SSN). Implemented in a 40-nm CMOS process, the × 16 tri-modal interface achieves an energy efficiency of better than 5.0 mW/Gbps per data link at 12.8 Gbps. |
| Databáze: | OpenAIRE |
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