Design of dynamic-floating-gate technique for output ESD protection in deep-submicron CMOS technology
| Autor: | Jiin Chuan Wu, Hun Hsien Chang, Ming-Dou Ker |
|---|---|
| Rok vydání: | 1999 |
| Předmět: |
Engineering
business.industry Electrical engineering Hardware_PERFORMANCEANDRELIABILITY Condensed Matter Physics Buffer (optical fiber) Electronic Optical and Magnetic Materials PMOS logic CMOS Robustness (computer science) Hardware_INTEGRATEDCIRCUITS Materials Chemistry Electronic engineering Electrical and Electronic Engineering Cmos process business NMOS logic Output device Hardware_LOGICDESIGN |
| Zdroj: | Solid-State Electronics. 43:375-393 |
| ISSN: | 0038-1101 |
| DOI: | 10.1016/s0038-1101(98)00262-7 |
| Popis: | A novel dynamic-floating-gate technique is proposed to improve ESD robustness of the CMOS output buffers with small driving/sinking currents. This dynamic-floating-gate design can effectively solve the ESD protection issue which is due to the different circuit connections on the output devices. By adding suitable time delay to dynamically float the gates of the output NMOS/PMOS devices which are originally unused in the output buffer, the human-body-model (machine-model) ESD failure threshold of a 2-mA output buffer can be practically improved from the original 1.0 kV (100 V) up to greater than 8 kV (1500 V) in a 0.35-μm bulk CMOS process. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|
Full Text from ScienceDirect