| Popis: |
In this paper, we talk about the short- and long-term implications of ignoring the relationship between the chip, package and PCB during I/O planning and how these issues will manifest themselves as we move toward 65 and 45nm technology.It also introduces a whole new approach to chip/package I/O planning and optimization. This new approach simultaneously synthesizes the entire interconnect from the I/O driver to the package ball and establishes an interconnect plan that is optimized for both chip and package. |
