Design, fabrication and characterization of multi-guard-ring furnished p+n−n+ silicon strip detectors for future HEP experiments
| Autor: | Ashutosh Bhardwaj, Kirti Ranjan, K. Lalwani, Ranjeet Dalal, Geetika Jain |
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| Rok vydání: | 2016 |
| Předmět: |
010302 applied physics
Physics Nuclear and High Energy Physics Large Hadron Collider Fabrication International Linear Collider Physics::Instrumentation and Detectors business.industry Detector Nanotechnology 02 engineering and technology STRIPS 021001 nanoscience & nanotechnology 01 natural sciences law.invention law 0103 physical sciences Optoelectronics Breakdown voltage High Energy Physics::Experiment 0210 nano-technology business Instrumentation Compact Muon Solenoid Voltage |
| Zdroj: | Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment. 824:428-431 |
| ISSN: | 0168-9002 |
| Popis: | Si detectors, in various configurations (strips and pixels), have been playing a key role in High Energy Physics (HEP) experiments due to their excellent vertexing and high precision tracking information. In future HEP experiments like upgrade of the Compact Muon Solenoid experiment (CMS) at the Large Hadron Collider (LHC), CERN and the proposed International Linear Collider (ILC), the Si tracking detectors will be operated in a very harsh radiation environment, which leads to both surface and bulk damage in Si detectors which in turn changes their electrical properties, i.e. change in the full depletion voltage, increase in the leakage current and decrease in the charge collection efficiency. In order to achieve the long term durability of Si-detectors in future HEP experiments, it is required to operate these detectors at very high reverse biases, beyond the full depletion voltage, thus requiring higher detector breakdown voltage. Delhi University (DU) is involved in the design, fabrication and characterization of multi-guard-ring furnished ac-coupled, single sided, p + n − n + Si strip detectors for future HEP experiments. The design has been optimized using a two-dimensional numerical device simulation program (TCAD-Silvaco). The Si strip detectors are fabricated with eight-layers mask process using the planar fabrication technology by Bharat Electronic Lab (BEL), India. Further an electrical characterization set-up is established at DU to ensure the quality performance of fabricated Si strip detectors and test structures. In this work measurement results on non irradiated Si Strip detectors and test structures with multi-guard-rings using Current Voltage (IV) and Capacitance Voltage (CV) characterization set-ups are discussed. The effect of various design parameters, for example guard-ring spacing, number of guard-rings and metal overhang on breakdown voltage of test structures have been studied. |
| Databáze: | OpenAIRE |
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