| Autor: |
George S. Tselikis, S. Tompros, J. Giamniadakis, S. Hontas, Dimitrios Loukatos, S. Andritsos, N. Mitrou |
| Rok vydání: |
2002 |
| Předmět: |
|
| Zdroj: |
ISCC |
| DOI: |
10.1109/iscc.1998.702477 |
| Popis: |
In this paper the design and the implementation of an ATM traffic generator system is presented. The basic principles of this document follow the architecture presented in Hontas et al. (1997). It is a PC-based system with a careful allocation of functions between hardware and software, in a way that it can work on-line at full-speed (155.52 Mbps) and, on the other hand, be flexible enough to emulate a wide range of ATM traffic profiles (VBR and CBR). The system is composed of a basic traffic generator and ATM signalling core card and four peripheral cards for the support of different physical interfaces. The architecture of the core card is open to any future modifications concerning signalling and functionality. The software of the system is running under Windows NT. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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