Fully Self-Aligned Via Integration for Interconnect Scaling Beyond 3nm Node

Autor:	H.P. Chen, Y.H. Wu, H.Y. Huang, C.H. Tsai, S.K. Lee, C.C. Lee, T.H. Wei, H.C. Yao, Y.C. Wang, C.Y. Liao, H.K. Chang, C.W. Lu, Winston S. Shue, Min Cao
Rok vydání:	2021
Zdroj:	2021 IEEE International Electron Devices Meeting (IEDM).
DOI:	10.1109/iedm19574.2021.9720600
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::41140a01a34304bcb6f9f1861b6a0e1b https://doi.org/10.1109/iedm19574.2021.9720600 Zobrazit plný text záznamu