Design of a Parallel VLSI Processor for Road Extraction Based on Logic-in-Memory Architecture

Autor:	Takahiro Hanyu, Michitaka Kameyama, Takao Kudoh
Rok vydání:	2000
Předmět:	Very-large-scale integration Parallel processing (DSP implementation) Computer architecture Computer science law Memory architecture A* search algorithm Architecture Bottleneck AND gate Data transmission law.invention
Zdroj:	Transactions of the Society of Instrument and Control Engineers. 36:1009-1018
ISSN:	0453-4654
DOI:	10.9746/sicetr1965.36.1009
Popis:	This paper describes the design of a road extraction VLSI (Very Large Scale Integration) processor that is designed to keep the data transfer bottleneck between processing elements to a minimum. It involves a algorithm that is based on parallel processing and logic- in-memory architecture.
Databáze:	OpenAIRE
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