A 600-MHz VLIW DSP
Autor: | S. Mullinnix, R. Simar, J. Apostol, Sanjive Agarwala, Luong Tan Nguyen, Lewis Nardini, Jerald G. Leach, Anthony M. Hill, M. Krishnan, Duc Quang Bui, Anthony J. Lell, P. Koeppen, N. Common, Timothy D. Anderson, Jeremiah E. Golston, P. Groves, P. Wiley, Raguram Damodaran, H. Mahmood, M.D. Ales, Quang-Dieu An, N.S. Nagaraj, Abhijeet Ashok Chachad, Arjun Rajagopal, Manisha Agarwala, David Hoyle, Roger K. Castille, Maria B. H. Gill |
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Rok vydání: | 2002 |
Předmět: |
Standard cell
Very-large-scale integration Digital signal processor business.industry Computer science Circuit design Bandwidth (signal processing) Transistor Hardware_PERFORMANCEANDRELIABILITY Integrated circuit design Chip law.invention Very long instruction word law Embedded system High-level synthesis Low-power electronics Hardware_INTEGRATEDCIRCUITS Hardware_ARITHMETICANDLOGICSTRUCTURES Electrical and Electronic Engineering business Digital signal processing |
Zdroj: | IEEE Journal of Solid-State Circuits. 37:1532-1544 |
ISSN: | 0018-9200 |
DOI: | 10.1109/jssc.2002.803954 |
Popis: | A 600-MHz VLIW digital signal processor (DSP) delivers 4800 MIPS, 2400 (16 b) or 4800 (8 b) million multiply accumulates (MMACs) at 0.3 mW/MMAC (16 b). The chip has 64M transistors and dissipates 719 mW at 600 MHz and 1.2 V, and 200 mW at 300 MHz and 0.9 V. It has an eight-way VLIW DSP core, a two-level memory system, and an I/O bandwidth of 2.4 GB/s. The chip integrates a c64X DSP core with Viterbi and turbo decoders. Architectural and circuit design approaches to achieve high performance and low power using a semi-custom standard cell methodology, while maintaining backward compatibility, are described. The chip is implemented in a 0.13-/spl mu/m CMOS process with six layers of copper interconnect. |
Databáze: | OpenAIRE |
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