| Popis: |
Power in Watts of the chip, per unit area is growing exponentially in the electronic industry. At the same time, thermal problems becoming side effects of huge power consumption. Continuous efforts are getting made to remove the thermal problems of electronic packaging and systems. Thermal problems if not alleviated or suppressed, will lead the dielectric breakdown, electromigration, material creep, thermal cycling, chemical reactions, board warpage, performance drift, indirect heating, and many more problems. Likewise, a dedicated Power Delivery/distribution Network (PDN), can deliver the power to the chip base, this paper has introduced a new methodology of a dedicated Thermal Collection Network (TCN) in the same Back End Of Line (BEOL) area of the System in Package (SiP), System on Chip (SOC) and any other power-consuming chips. Adding a Thermal Through Silicon Via (TTSV) is another advantage in it. Using such an apparatus or methodology connected to TTSV will quickly pump-up the thermal energy to the heat-sink-fan assembly. Hence, preempting of heat from its sources can manage the thermal problems inside the chips or 3-D IC structures. The methodology uses the same copper metal stripes inside the Inter-Layer/Level-Dielectric (ILD), which will not lead to any extra copper to introduce more Coefficient of Thermal Efficiency (CTE) mismatch problems. It would be considered as one among the other metal stripes. The experimental results using the Finite Element Method (FEM) tool shown that 32% heat suction occurs in the TCNs, in monolithic ICs, and 11% in 3-D IC structures, compared to without such an approach. The junction temperature remained at 35%, with and without such an approach, in 3-D IC structures. This might lead to a new methodology for designing electronic chips and 3-D IC structures, in the future. |
