Logic Synthesis for FPGAs of Interpreted Petri Net with Common Operation Memory

Autor:	Marian Adamski, Arkadiusz Bukowiec
Rok vydání:	2012
Předmět:	Combinational logic Sequential logic Logic synthesis Theoretical computer science Computer science Logic gate General Medicine Petri net Arithmetic Field-programmable gate array Hardware_LOGICDESIGN Logic optimization Asynchronous circuit
Zdroj:	PDeS
ISSN:	1474-6670
DOI:	10.3182/20120523-3-cz-3015.00013
Popis:	The method of synthesis of the logic circuit of interpreted Petri net is proposed in this paper. Proposed method is based on the minimal encoding of places. Places are encoded in subsets. Each subset is represented by one color of colored Petri net. Operations assigned to places are placed in memory. It leads to realization of logic circuit in two-level architecture, where the combinational circuit of first level is responsible for firing transitions and the second level memory is responsible for the generation of operations. Such approach allows balanced usage of different kinds of resources available in modern FPGAs.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::40d21cccb3ee5b2daabe86ebe4f06793 https://doi.org/10.3182/20120523-3-cz-3015.00013 Zobrazit plný text záznamu