Prediction of product yield distributions from wafer parametric measurements of CMOS circuits
| Autor: | J. Heuy, L. Mizrukhin, S. Mehta |
|---|---|
| Rok vydání: | 1992 |
| Předmět: |
Engineering
Yield (engineering) business.industry Semiconductor device modeling Hardware_PERFORMANCEANDRELIABILITY Integrated circuit Condensed Matter Physics Industrial and Manufacturing Engineering Standard deviation Electronic Optical and Magnetic Materials law.invention PMOS logic CMOS law Hardware_INTEGRATEDCIRCUITS Electronic engineering Electrical and Electronic Engineering business NMOS logic Hardware_LOGICDESIGN Electronic circuit |
| Zdroj: | IEEE Transactions on Semiconductor Manufacturing. 5:88-93 |
| ISSN: | 0894-6507 |
| DOI: | 10.1109/66.136268 |
| Popis: | A technique for predicting the yield distribution of CMOS circuits based on electrical parameter distributions is presented. This technique uses the mean and standard deviation of the measured threshold voltage and mobility of NMOS and PMOS transistors to project the yield of the circuit in a specified design window. The method thus provides a quantitative means of carrying out tradeoffs between design windows and final product yield. > |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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