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The hierarchical design for testability (DFT) rule checker Cerberus has been developed to handle hierarchical circuits supporting a variety of scan structures with different types of scannable storage devices. Cerberus utilizes a general approach to testability rule checking and is part of a computer-aided engineering system to integrate design and test. Cerberus consists of the following components: an extractor to provide a levelized directed graph representation from a circuit netlist, a preprocessor to provide acyclic graphs and for topological sorting of circuit nodes, a rule checker nucleus to perform the DFT verification process hierarchically, and a protocol generator to output the rule-checker results in a user-friendly representation. > |
