High-Level Synthesis of VLSI Processors for Intelligent Integrated Systems Based on Logic-in-Memory Structure
| Autor: | Michitaka Kameyama, Takao Kudoh |
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| Rok vydání: | 2003 |
| Předmět: | |
| Zdroj: | IEEJ Transactions on Electronics, Information and Systems. 123:1374-1381 |
| ISSN: | 1348-8155 0385-4221 |
| DOI: | 10.1541/ieejeiss.123.1374 |
| Popis: | One of the most serious problems in recent VLSI systems is data transfer bottleneck between memories and processing elements. To solve the problem, a model of highly parallel VLSI processors for intelligent integrated systems is presented. A logic-in-memory module composed of a processing element, a register and a local memory is defined as a basic building block to form a regular parallel structure. The data transfer between adjacent modules are done simply in a single clock period by a shift-register chain.A high-level synthesis method is discussed on the hardware model, when a data-dependency graph corresponding to a processing algorithm is given. We must simultaneously consider both scheduling and allocation for the time optimization problem under a constraint of an chip area. That is, we consider the best scheduling together with allocation such that the processing time becomes minimum under a constraint of a fixed number of modules. Not only an exhaustive enumeration method but also a branch-and-bound method is proposed for the problem. As a result, it is made clear that the proposed high-level synthesis method is very effective to design special-purpose VLSI processors free from data transfer bottleneck. |
| Databáze: | OpenAIRE |
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