In-cache pre-processing and decode mechanisms for fine grain parallelism in SCISM
| Autor: | James Edward Phillips, Nadeem Malik, Bartholomew Blaner, Stamatis Vassiliadis, Richard J. Eickemeyer |
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| Rok vydání: | 2002 |
| Předmět: |
Out-of-order execution
Reduced instruction set computing CPU cache Computer science Fine grain parallelism Data parallelism Fetch Task parallelism Parallel computing Instruction set Computer architecture Parallel processing (DSP implementation) Preprocessor Cache Implicit parallelism Instruction-level parallelism |
| Zdroj: | Proceedings of Phoenix Conference on Computers and Communications. |
| Popis: | A study was initiated that investigated detractors to parallelism and implementation constraints associated with the critical paths in the design of fine grain parallel machines. The outcome of the research has been a new machine organization that facilitates and improves parallel instruction issue and possible increases in cycle time and by improving the instruction-level parallelism, using specialized hardware. The authors describe the attributes of the proposed machine organization related to the analysis of instruction sequences for the parallel issue and execution. They also describe the permanent preprocessing in the cache that allows for the determination of instructions for parallel execution prior to the instruction fetch and issues. > |
| Databáze: | OpenAIRE |
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