A 12-b 40-MS/s Calibration-Free SAR ADC
| Autor: | Huan-Jui Hu, Li-Jen Chang, Chun-Po Huang, Hwa-An Tseng, Chih-Huei Hou, Ya-Ting Shyu, Chung-Wei Hsu, Chih-Yuan Kung, Soon-Jyh Chang |
|---|---|
| Rok vydání: | 2018 |
| Předmět: |
0209 industrial biotechnology
Computer science 020208 electrical & electronic engineering Linearity Successive approximation ADC 02 engineering and technology Converters law.invention Capacitor 020901 industrial engineering & automation CMOS law Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Electronic engineering Calibration Oversampling Electrical and Electronic Engineering Decoding methods |
| Zdroj: | IEEE Transactions on Circuits and Systems I: Regular Papers. 65:881-890 |
| ISSN: | 1558-0806 1549-8328 |
| DOI: | 10.1109/tcsi.2017.2771364 |
| Popis: | This paper presents a new circuit technique named residue oversampling, which is suitable for high-resolution analog-to-digital converters (ADCs). By adopting this technique and simplifying the dynamic element matching, the impacts of capacitor mismatch and noise upon the successive-approximation register ADCs are reduced significantly without calibrations. The proof-of-concept prototype was fabricated in TSMC 40-nm CMOS technology. At 40-MS/s and 10-MS/s sampling rates, the measured peak signal-to-noise and distortion ratios are 66.84 and 69.78 dB, respectively. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|