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Compaan is a software tool that is capable of automatically translating nested loop programs, written in Matlab, into parallel process network descriptions suitable for implementation in hardware. In this article, we show a methodology and tool to convert theseprocess networks into FPGA implementations. We will show that we can in principleobtain high performing realizations in a fraction of the design time currentlyemployed to realize a parameterized implementation. This allows us to rapidlyexplore a range of transformations, such as loop unrolling and skewing, togenerate a circuit that meets the requirements of a particular application.The QR decomposition algorithm is used to demonstrate the capability of thetool. We present results showing how the number of clock cycles and calculations-per-secondvary with these transformations using a simple implementation of the functionunits. We also provide an indication of what we expect to achieve in the nearfuture once the tools are completed and applied the transformations to parallel,highly pipelined implementations of the function units. |
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