Process-optimization for sub-30 ps BiCMOS technologies for mixed ECL/CMOS applications
| Autor: | P. Weger, M. Kerber, H. Klose, R. Kopl, M. Ohnemus, J. Weng, T.F. Meister |
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| Rok vydání: | 2002 |
| Předmět: |
Engineering
business.industry Depletion-load NMOS logic Logic family Electrical engineering Mixed-signal integrated circuit Hardware_PERFORMANCEANDRELIABILITY BiCMOS Emitter-coupled logic Resistor–transistor logic Integrated injection logic CMOS Hardware_INTEGRATEDCIRCUITS Electronic engineering business Hardware_LOGICDESIGN |
| Zdroj: | International Electron Devices Meeting 1991 [Technical Digest]. |
| DOI: | 10.1109/iedm.1991.235417 |
| Popis: | The authors present a 0.8 mu m BiCMOS technology for high-performance digital applications. The underlying optimization strategy to trade off both bipolar vs. CMOS speed and cutoff-frequency vs. collector-emitter breakdown voltage is described. Based on this approach 23.5 GHz cutoff frequency and 28 ps CML gate-delay times could be obtained for the bipolar device, making this technology perfectly suited for mixed CMOS/ECL (emitter-coupled logic) types of applications. This is additionally proved by high-speed benchmark circuits such as 2:1 frequency dividers operating up to 13.5 GHz. > |
| Databáze: | OpenAIRE |
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