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Discusses a VLSI-based multiprocessor architecture for real-time processing of video coding applications. The architecture consists of multiple identical processing elements and is characterized as MIMD (multiple instruction multiple data). The architecture of a processing element is based on a standard processor core, e.g., a RISC processor, and a low-level coprocessor. The low-level coprocessor is adapted to parallel processing of convolution like operations. The performance of the architecture is discussed with respect to the processing time for hybrid coding algorithms as well as to the required silicon area. > |
