22 nm technology compatible fully functional 0.1 μm2 6T-SRAM cell

Autor:	Sanjay Mehta, R. H. Kim, V. Basker, Sean D. Burns, Kangguo Cheng, Yu Zhu, A. Ebert, Scott Halle, Chen Jia, Karen Petrillo, Soon-Cheon Seo, D. Horak, Vamsi Paruchuri, R. Johnson, T. Levin, Hemanth Jagannathan, J. Faltermeier, Jason E. Cummings, T. Sparks, M. Raymond, Wilfried Haensch, Lahir Shaik Adam, Su Chen Fan, Amit Kumar, N. Berliner, Bala S. Haran, Terry A. Spooner, S. Kanakasabapathy, Stefan Schmitz, J. Kuss, Josephine B. Chang, Thomas S. Kanarsky, Lisa F. Edge, Chiew-seng Koay, Charles W. Koburger, John C. Arnold, S. Holmes, Bruce B. Doris, Erin Mclellan, D. LaTulipe, Martin Burkhardt, D. McHerron, S. Paparao, Donald F. Canaperi, M. Smalley, James J. Demarest, Matt Colburn
Rok vydání:	2008
Předmět:	Materials science business.industry Annealing (metallurgy) Transistor Copper interconnect Electrical engineering law.invention chemistry.chemical_compound chemistry law Logic gate Silicide Optoelectronics Node (circuits) business Metal gate Immersion lithography
Zdroj:	2008 IEEE International Electron Devices Meeting.
Popis:	We demonstrate 22 nm node technology compatible, fully functional 0.1 mum2 6T-SRAM cell using high-NA immersion lithography and state-of-the-art 300 mm tooling. The cell exhibits a static noise margin (SNM) of 220 mV at Vdd=0.9 V. We also present a 0.09 mum2 cell with SNM of 160 mV at Vdd=0.9 V demonstrating the scalability of the design with the same layout. This is the world's smallest 6T-SRAM cell. Key enablers include band edge high-kappa metal gate stacks, transistors with 25 nm gate lengths, thin spacers, novel co-implants, advanced activation techniques, extremely thin silicide, and damascene copper contacts.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::3f2618a1a98015406797d8aa44d360c1 https://doi.org/10.1109/iedm.2008.4796769 Zobrazit plný text záznamu