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This paper describes the design and operation of a single-event upset (SEU) immune CMOS logic-configuration data cell design for reprogrammable digital logic circuits. The configuration data cell design is based on proven concepts. The data cell consistently assumes a prescribed data state when powered-up thus minimizing turn-on power dissipation and preventing data bus contention. Control signal pulses can be applied to selectively read the state of a data cell and to selectively set a data cell to a desired data state. Regardless of the data being stored, the data cell is SEU-immune. Circuit simulations are used to verify the full operation and SEU-immunity of the data cell design, even at worst case conditions. |