| Autor: |
J.W. Baggs, J.D. Mis, P.A. Magill, Glenn A. Rinne, W.C. Machon |
| Rok vydání: |
2002 |
| Předmět: |
|
| Zdroj: |
Proceedings. 4th International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces (Cat. No.98EX153). |
| DOI: |
10.1109/isapm.1998.664436 |
| Popis: |
Packaging of electronic components is in a transitional phase due to the relentless progress of transistor integration that is going on in the semiconductor environment. While all manufacturers may want to transition directly to flip chip, for a number of reasons, that may not always be possible. There are areas, in electronic manufacturing, that are under pressure to increase packaging density and reduce size and weight. For these products, solutions that allow manufacturers to operate in an environment that is familiar while additional infrastructure for full flip chip is being implemented are valuable. Packaging solutions of this type are referred to as chip scale packages. The use of redistributed lines in the solder provides for the smallest possible chip scale package. This particular methodology for producing a chip scale package meets all of the criteria established for evaluating the worthiness of a CSP and can be manufactured today at the lowest possible cost. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
|
