CSAM: A clock skew-aware aging mitigation technique
| Autor: | B. Eghbalkhah, Massoud Pedram, Mehdi Kamal, Mohammad Bagher Ghaznavi-Ghoushchi, Ali Afzali-Kusha |
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| Rok vydání: | 2015 |
| Předmět: |
Engineering
Optimization problem business.industry Clock rate NAND gate Clock gating Condensed Matter Physics Clock skew Atomic and Molecular Physics and Optics Surfaces Coatings and Films Electronic Optical and Magnetic Materials Benchmark (computing) Electronic engineering Node (circuits) Electrical and Electronic Engineering Safety Risk Reliability and Quality business CPU multiplier |
| Zdroj: | Microelectronics Reliability. 55:282-290 |
| ISSN: | 0026-2714 |
| Popis: | In this work, we propose a clock skew-aware aging mitigation (CSAM) technique which considers the effect of asymmetric aging both on logic path and clock tree together. Simultaneous consideration of both parts in the design optimization problem enables us to reduce the area overhead while increasing the lifetime. For the aging mitigation of the logic path, we make use of both internal node control (INC) and input vector control (IVC) techniques while, for the clock tree circuits, a proper choice between NAND or NOR based integrated clock gating (ICG) cell is made. The optimization may be performed based on two objective functions of maximizing lifetime or minimizing the area overhead for a predetermined clock frequency and lifetime. To assess the efficacy of the proposed technique, we compared the lifetimes and area overheads for a set of circuits from ISCAS89 and ITC99 benchmark suites when CSAM and conventional techniques are used. The results, obtained using SPICE simulations for the circuits in a 45-nm technology, reveals that an average lifetime improvement of 34% and an average area overhead reduction of 25.7% for the two objective functions, respectively. |
| Databáze: | OpenAIRE |
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