A bipolar load CMOS SRAM cell for embedded applications
| Autor: | A. Shubat, G.A. Rezvani, R. Irani, Anirban Roy, R. Kazerounian, Cary Y. Yang, B. Eitan |
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| Rok vydání: | 1995 |
| Předmět: |
Engineering
business.industry Transistor Bipolar junction transistor Electrical engineering Hardware_PERFORMANCEANDRELIABILITY Electronic Optical and Magnetic Materials law.invention CMOS law Memory architecture Hardware_INTEGRATEDCIRCUITS Electronic engineering Static random-access memory Electrical and Electronic Engineering Current (fluid) business Electrical impedance NMOS logic |
| Zdroj: | IEEE Electron Device Letters. 16:169-171 |
| ISSN: | 1558-0563 0741-3106 |
| DOI: | 10.1109/55.382229 |
| Popis: | This paper presents a new SRAM cell concept which offers cell scaling without requiring complicated, specialized processing technology. The proposed cell utilizes a bipolar transistor in an open-base (base is floating) configuration as a simple means of realizing a high impedance load element. The Bipolar Transistor Load (BTL) is designed such that its open base current (the holding current) is always large enough to compensate for the NMOS pull-down transistor leakage current. The load holding current and the pull-down transistor leakage current are based on the same physical mechanism, namely thermal generation, as a result the load exhibits current tracking properties over varying process and temperature conditions. The cell size is 72 /spl mu/m/sup 2/ with typical 0.8 /spl mu/m design rules, which is about a 60% reduction as compared to a standard 6-T full CMOS cell. The operating properties of the BTL cell were studied analytically and characterized experimentally. The BTL SRAM module can be easily integrated as part of any CMOS process with minimal additional processing steps. > |
| Databáze: | OpenAIRE |
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