Modeling of Variation in Submicrometer CMOS ULSI Technologies
| Autor: | Noah Zamdmer, Josef S. Watts, Richard Q. Williams, Jean-Olivier Plouchart, Scott K. Springer, E. J. Nowak, Ning Lu, Sungjae Lee |
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| Rok vydání: | 2006 |
| Předmět: |
Engineering
Tolerance analysis business.industry Circuit design Transistor Design flow Electrical engineering Semiconductor device modeling Integrated circuit Electronic Optical and Magnetic Materials law.invention CMOS law Hardware_INTEGRATEDCIRCUITS Electronic engineering Node (circuits) Electrical and Electronic Engineering business |
| Zdroj: | IEEE Transactions on Electron Devices. 53:2168-2178 |
| ISSN: | 1557-9646 0018-9383 |
| DOI: | 10.1109/ted.2006.880165 |
| Popis: | The scaling of semiconductor technologies from 90- to 45-nm nodes highlights the need for accurate and predictive compact models that address the regime where small-scale physical effects become dominant. These demanding requirements on compact models extend beyond the core model to a suite of design tools that include extraction tools and statistical methods to account for unpredictable variation (e.g., random dopant fluctuations and polysilicon linewidth variation) and predictable variation (e.g., transistor response differences that are layout dependent). Layout-dependent or local environment differences are driven by factors such as lithography and novel performance-enhancing process techniques such as dual-stress nitride liner films. Sources of variation such as rapid thermal annealing temperature, low-frequency noise, and modeling of back-end-of-line elements need to be considered. The modeling of intradie and interdie variations, updated for small geometries, should be properly positioned in the design flow. This paper presents the challenges and results of compact modeling at the 65-nm node and beyond |
| Databáze: | OpenAIRE |
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